Recent advances in data-intensive applications, including AI training and inference, have increased the demand for high-performance memory and storage solutions. To meet the growing requirement for higher memory capacity and reduce cost per bit, a cross-point array architecture is being explored. This approach relies on a two-terminal non-linear selector device instead of a silicon-based MOSFET transistor to address selected memory cells. Various devices, such as Ovonic threshold switches (OTS) and Schottky diodes, have been investigated for this function.